Department of Computer Science, National Chiao-Tung University

IOC5114 Electronic System Level Design and Modeling

Ÿ             Time of Offering: Spring, 2008

Ÿ             Level: Elective for graduate students and undergraduate students of third or fourth year.

Ÿ             Instructor

­             Prof. Wen-Hsiao Peng (彭文孝)

­             E-mail:

­             Office: EC431 (工三館 431)

­             Phone: Ext56625

­             Lab: Multimedia Architecture and Processing Laboratory (MAPL)

­             URL:

Ÿ             Course Homepage


Ÿ             Lectures

­             The course meets on Tuesdays from 3:40pm to 4:30pm and Fridays from 10:10am to 12:00pm in ED 027 (工程四館 027).

Ÿ             Course Outline (Subject to Change)

­             (1 week) Introduction of SoC Design Flow

w            Overview of SoC Design Flow.

w            Necessity of Transaction Level Modeling in the SoC Design Flow.

­             (2 weeks) Transaction Level Modeling (TLM)

w            Concepts of TLMs.

w            TLM-based SoC Design Methodology.

w            TLM at Different Abstraction Levels: Accuracy versus Speed.

­             (3 weeks) Transaction Level Modeling in SystemC

w            Fundamentals of SystemC.

w            Interface, Port, Channel, and Process.

w            Separation of Communication and Computation.

w            Progressive Refinement of TLM Model.

w            Case Study: Simple Bus Design.

w            TLM API in SystemC

­             (3 weeks) Algorithm and Architecture Co-design

w            Rationale of Algorithm and Architecture Co-design.

w            Extraction of Complexity Information from Algorithms.

w            Algorithm/Architecture Design Space Exploration.

w            Case Study: A Reconfigurable Video Transcoder

­             (3 weeks) Transaction Level Modeling in Platform-based Design

w            ARM 9 Processor and AMBA Bus.

w            Bus Arbitration Policy and System Performance.

w            Dedicated Hardware and Firmware.

w            Control and Status Registers.

w            External Memory Interface and Direct Memory Access.

w            Case Study: JPEG Codec.

­             (2 weeks) Case Study: H.264/AVC Decoder Designed for High Definition Applications.

w            Fundamentals of H.264/AVC.

w            Exploration of Design Spaces with TLM.

w            Performance Analysis.

­             (2 weeks) ESL Design from Industrial Perspective (by Andes R&D)

w            ESL Design Flow in Andes CPU Development.

w            HW/SW Co-Design with Andes In-house ESL Tools.

Ÿ             Text Books

­             Lecture Notes

w            Prof. Wen-Hsiao Peng (彭文孝), Dept. of Computer Science, National Chiao-Tung University

w            Prof. Gwo Giun Lee (李國君), Dept. of Electrical Engineering, National Cheng-Kung University

­             F. Ghenassia, “Transaction-Level Modeling with SystemC : TLM Concepts and Applications for Embedded Systems”, 1st Edition, Springer, 2005. (ISBN: 0387262326)

Ÿ             Reference Books and Links

­             T. Grotker, S. Liao, G. Martin, and S. Swan, “System Design with SystemC”, 1st Edition, Kluwer Academic, 2002. (ISBN: 1402070721) (Accessible from Net Library)

­             D. Black and J. Donovan, “SystemC: From the Ground Up”, 1st Edition, Springer, 2004. (ISBN: 1402079885) (Accessible from Net Library)

­             A. Clouard, K. Jain, F. Ghenassia, L. Maillet-Contoz, and J. Strassen, “SystemC: Methodologies and Applications, Kluwer Academic, 2003. (ISBN: 1402074794) (Accessible from Net Library)

­             J. Bhasker, “A SystemC Premier, 1st Edition, Star Galaxy Publishing, 2004. (ISBN 0965039188)

­             OSCI Web Page:

­             Net Library: 

Ÿ             Grading Policy

­             50% Homeworks (Issued approximately once every 2~3 weeks).

·      Computer simulations.

·      Should be done individually, but discussions are encouraged.

­             50% Final Project.

·      Motion JPEG from Algorithm to RTL with ESL simulation on ConvergenSC

·      Work individually or as part of a team of 2-3 students.

·      Project grade based on (1) architecture design and simulation results 40%, (2) project report 30%, and (3) presentation 30%.

Ÿ             Office Hours

­             Tuesday/Friday after class in Engineering Building III Room 431.

­             Other time slots are also possible by appointments beforehand.

Ÿ             Teaching Assistant

­             李志宏


­             TEL: ext54232

Ÿ             Miscellaneous

­             4/28~5/02 – attending ISO/IEC MPEG Meeting.